1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and particularly relates to a method of fabricating an n-channel metal-oxide-semiconductor (NMOS) transistor which may avoid nickel silicide piping phenomenon and etching through.
2. Description of the Prior Art
In a conventional MOS transistor manufacturing process, during formation of source/drain regions, dopants are sent into a substrate in high speed by implantation process using a gate structure and a spacer as a mask. The crystal lattice of the substrate tends to be damaged from such high speed impact and an annealing process is usually needed to recover the damaged lattice after the implantation. However, during the recovery of the lattice, dislocation easily takes place, especially in a heavily doped region, such as the place of the substrate downward from the edge of the mask (i.e. spacer) in a depth of 200 to 300 angstrom from the surface of the substrate, due to stress. The dislocation usually occurs in an NMOS process, because n-type dopants, such as arsenic, used in the NMOS process have a larger atomic size than p-type dopants, such as boron, used in PMOS process and easily damage the silicon lattice.
Furthermore, in conventional MOS transistor processes, a metal silicide is often formed over the surface of the gate structure and the source/drain region to benefit the formation of contact plugs to reduce sheet resistance. Currently, the process known as self-aligned silicide (salicide) process has been widely utilized to fabricate silicide materials, in which a metal layer is subject to a rapid thermal process to allow the metal atoms to diffuse into the silicon substrate for reaction with the silicon in the source/drain region. Thus, if a dislocation as aforesaid exists in the substrate lattice, it is easily to cause piping phenomenon, and, that is, the metal atoms easily react with silicon along the dislocation. As a result, the distance between the p-n junction of the source/drain and the silicon substrate and the metal silicide layer will be overly short, and it is much worse that the metal silicide often comes in contact directly with the substrate to result in failure of the device. As the schematic diagram shown in FIG. 1, a gate 12, a spacer 14 and source/drain regions 16 and 18 are disposed on a silicon substrate 10. Dislocations 20 and 22 exist in the silicon substrate 10. Thus, if a nickel silicide layer 24 having a conventional thickness is formed on the source/drain region 16, a piping effect will occur since the distance between the nickel silicide layer 24 and the dislocation place 20 is overly short. However, if it is considered to reduce the thickness of the nickel silicide layer, as shown by the nickel silicide layer 26 on the source/drain region 18, to increase the distance for avoiding piping, the nickel silicide layer 26 tends to be etched through during the etching process for formation of the contact plug 28 due to its small thickness, such that the contact plug 28 directly contacts the source/drain region 18, resulting in high contact resistance.
Therefore, there is still a need for a novel NMOS fabrication method for preventing the aforesaid problems.